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GTL2010
10-bit bidirectional low voltage translator
Rev. 06 -- 3 March 2008 Product data sheet
1. General description
The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2010 provides 10 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 1.0 V and 5.0 V without use of a direction pin. When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control. All transistors have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the transistors is symmetrical. Because all transistors in the device are identical, SREF and DREF can be located on any of the other ten matched Sn/Dn transistors, allowing for easier board layout. The translator's transistors provide excellent ESD protection to lower voltage devices and at the same time protect less ESD-resistant devices.
2. Features
I 10-bit bidirectional low voltage translator I Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels I Provides bidirectional voltage translation with no direction pin I Low 6.5 ON-state resistance (Ron) between input and output pins (Sn/Dn) I Supports hot insertion I No power supply required: will not latch up I 5 V tolerant inputs I Low standby current I Flow-through pinout for ease of printed-circuit board trace routing I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Packages offered: TSSOP24, HVQFN24
NXP Semiconductors
GTL2010
10-bit bidirectional low voltage translator
3. Applications
I Any application that requires bidirectional or unidirectional voltage level translation from any voltage from 1.0 V to 5.0 V to any voltage from 1.0 V to 5.0 V I The open-drain construction with no direction pin is ideal for bidirectional low voltage (for example, 1.0 V, 1.2 V, 1.5 V or 1.8 V) processor I2C-bus port translation to the normal 3.3 V and/or 5.0 V I2C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels
4. Ordering information
Table 1. Ordering information Package Name GTL2010PW GTL2010BS TSSOP24 HVQFN24 Description plastic thin shrink small outline package; 24 leads; body width 4.4 mm Version SOT355-1 Type number
plastic thermal enhanced very thin quad flat package; SOT616-1 no leads; 24 terminals; body 4 x 4 x 0.85 mm
4.1 Ordering options
Table 2. Ordering options Topside mark GTL2010 2010 Temperature range -40 C to +85 C -40 C to +85 C Type number GTL2010PW GTL2010BS
5. Functional diagram
DREF GREF D1 D10
SREF
S1
S10
002aac059
Fig 1.
Functional diagram
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6. Pinning information
6.1 Pinning
21 GREF
SREF S1 S2 S3 S4 S5 S6 S7
2 3 4 5 6 7 8 9
23 DREF 22 D1 21 D2 20 D3 19 D4 18 D5 17 D6 16 D7 15 D8 14 D9 13 D10
002aac057
S2 S3 S4 S5 S6 S7
1 2 3 4 5 6 D10 10 D9 11 D8 12 7 8 9
19 D1 18 D2 17 D3 16 D4 15 D5 14 D6 13 D7
002aac058
GTL2010PW
24 S1
terminal 1 index area
GTL2010BS
S8 10 S9 11 S10 12
S8
S9
Transparent top view
Fig 2.
Pin configuration for TSSOP24
Fig 3.
Pin configuration for HVQFN24
6.2 Pin description
Table 3. Symbol GND SREF S1 to S10 D1 to D10 DREF GREF
[1]
Pin description Pin TSSOP24 1 2 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 HVQFN24 22[1] 23 ground (0 V) source of reference transistor Description
24, 1, 2, 3, 4, 5, 6, Port S1 to Port S10 7, 8, 9
22, 21, 20, 19, 18, 19, 18, 17, 16, 15, Port D1 to Port D10 17, 16, 15, 14, 13 14, 13, 12, 11, 10 23 24 20 21 drain of reference transistor gate of reference transistor
HVQFN24 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
GTL2010_6
S10
22 GND
GND
1
24 GREF
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20 DREF
23 SREF
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GTL2010
10-bit bidirectional low voltage translator
7. Functional description
Refer also to Figure 1 "Functional diagram".
7.1 Function selection
Table 4. Function selection, HIGH-to-LOW translation Assumes Dn is at the higher voltage level. H = HIGH voltage level; L = LOW voltage level; X = Don't care GREF[1] H H H L
[1] [2] [3] [4]
DREF H H H L
SREF[2] 0V VT VT 0 V - VT
Input Dn X H L X
Output Sn X VT X
[3]
Transistor off on on off
L[4]
GREF should be at least 1.5 V higher than SREF for best translator operation. VT is equal to the SREF voltage. Sn is not pulled up or pulled down. Sn follows the Dn input LOW.
Table 5. Function selection, LOW-to-HIGH translation Assumes Dn is at the higher voltage level. H = HIGH voltage level; L = LOW voltage level; X = Don't care GREF[1] H H H L
[1] [2] [3] [4]
DREF H H H L
SREF[2] 0V VT VT 0 V - VT
Input Sn X VT L X
Output Dn X H[3] L[4] X
Transistor off nearly off on off
GREF should be at least 1.5 V higher than SREF for best translator operation. VT is equal to the SREF voltage. Dn is pulled up to VCC through an external resistor. Dn follows the Sn input LOW.
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GTL2010
10-bit bidirectional low voltage translator
8. Application design-in information
8.1 Bidirectional translation
For the bidirectional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF input must be connected to DREF and both pins pulled to HIGH side VCC through a pull-up resistor (typically 200 k). A filter capacitor on DREF is recommended. The processor output can be totem pole or open-drain (pull-up resistors may be required) and the chip set output can be totem pole or open-drain (pull-up resistors are required to pull the Dn outputs to VCC). However, if either output is totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs must be controlled by some direction control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no direction control is needed. The opposite side of the reference transistor (SREF) is connected to the processor core power supply voltage. When DREF is connected through a 200 k resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to (VCC - 1.5 V), the output of each Sn has a maximum output voltage equal to SREF and the output of each Dn has a maximum output voltage equal to VCC.
1.8 V 1.5 V 1.2 V 1.0 V GND VCORE CPU I/O S2 SREF S1
5V
200 k
totem pole or open-drain I/O GREF DREF D1 CHIPSET I/O D2 VCC
increase bit size by using 10-bit GTL2010 or 22-bit GTL2000 VCC S3 S4 S5 Sn D3
3.3 V
CHIPSET I/O D4 D5 Dn
002aac060
Typical bidirectional voltage translation.
Fig 4.
Bidirectional translation to multiple higher voltage levels such as an I2C-bus application
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10-bit bidirectional low voltage translator
8.2 Unidirectional down translation
For unidirectional clamping, higher voltage to lower voltage, the GREF input must be connected to DREF and both pins pulled to the higher side VCC through a pull-up resistor (typically 200 k). A filter capacitor on DREF is recommended. Pull-up resistors are required if the chip set I/Os are open-drain. The opposite side of the reference transistor (SREF) is connected to the processor core supply voltage. When DREF is connected through a 200 k resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to (VCC - 1.5 V), the output of each Sn has a maximum output voltage equal to SREF.
1.8 V 1.5 V 1.2 V 1.0 V easy migration to lower voltage as processor geometry shrinks VCORE CPU I/O S2 GND SREF S1
5V
200 k
GREF DREF D1 CHIPSET I/O D2 totem pole I/O
002aac061
VCC
Typical unidirectional HIGH-to-LOW voltage translation.
Fig 5.
Unidirectional down translation to protect low voltage processor pins
8.3 Unidirectional up translation
For unidirectional up translation, lower voltage to higher voltage, the reference transistor is connected the same as for a down translation. A pull-up resistor is required on the higher voltage side (Dn or Sn) to get the full HIGH level, since the GTL-TVC device will only pass the reference source (SREF) voltage as a HIGH when doing an up translation. The driver on the lower voltage side only needs pull-up resistors if it is open-drain.
1.8 V 1.5 V 1.2 V 1.0 V easy migration to lower voltage as processor geometry shrinks VCORE CPU I/O S2 totem pole I/O or open-drain GND SREF S1
5V
200 k
GREF DREF D1 CHIPSET I/O D2 VCC
002aac062
Typical unidirectional LOW-to-HIGH voltage translation.
Fig 6.
Unidirectional down translation to protect low voltage processor pins
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10-bit bidirectional low voltage translator
8.4 Sizing pull-up resistor
The pull-up resistor value needs to limit the current through the pass transistor when it is in the `on' state to about 15 mA. This will guarantee a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage will also be higher in the `on' state. To set the current through each pass transistor at 15 mA, the pull-up resistor value is calculated as shown in Equation 1: pull-up voltage ( V ) - 0.35 V resistor value ( ) = -----------------------------------------------------------------------------0.015 A (1)
Table 6 summarizes resistor values for various reference voltages and currents at 15 mA and also at 10 mA and 3 mA. The resistor value shown in the + 10 % column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the GTL-TVC device at 0.175 V, although the 15 mA only applies to current flowing through the GTL-TVC device. See application note AN10145, "Bi-directional low voltage translators" for more information.
Table 6. Voltage 15 mA[2] Nominal 5.0 V 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V
[1] [2] [3]
Pull-up resistor values Pull-up resistor value ()[1] 10 mA[2] %[3] Nominal 465 295 215 145 115 85 + 10 %[3] 341 217 158 106 85 63 512 325 237 160 127 94 1550 983 717 483 383 283 3 mA[2] Nominal + 10 %[3] 1705 1082 788 532 422 312 + 10
310 197 143 97 77 57
Calculated for VOL = 0.35 V. Assumes output driver VOL = 0.175 V at stated current. + 10 % to compensate for VCC range and resistor tolerance.
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10-bit bidirectional low voltage translator
9. Limiting values
Table 7. Limiting values[1] In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VSREF VDREF VGREF VSn VDn IREFK ISK IDK IMAX Tstg
[1]
Parameter voltage on pin SREF voltage on pin DREF voltage on pin GREF voltage on port Sn voltage on port Dn diode current on reference pins diode current Port Sn diode current Port Dn clamp current per channel storage temperature
Conditions
[2] [2] [2] [2] [2]
Min -0.5 -0.5 -0.5 -0.5 -0.5 -65
Max +7.0 +7.0 +7.0 +7.0 +7.0 -50 -50 -50 128 +150
Unit V V V V V mA mA mA mA C
VI < 0 V VI < 0 V VI < 0 V channel in ON-state
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2]
10. Recommended operating conditions
Table 8. Symbol VI/O VSREF VDREF VGREF IPASS Tamb
[1]
Recommended operating conditions Parameter voltage on pin SREF voltage on pin DREF voltage on pin GREF pass transistor current ambient temperature operating in free air Conditions
[1]
Min 0 0 0 0 -40
Typ -
Max 5.5 5.5 5.5 5.5 64 +85
Unit V V V V mA C
voltage on an input/output pin Sn, Dn
VSREF VDREF - 1.5 V for best results in level shifting applications.
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10-bit bidirectional low voltage translator
11. Static characteristics
Table 9. Static characteristics Tamb = -40 C to +85 C, unless otherwise specified. Symbol VOL VIK ILI(G) Cig Cio(off) Cio(on) Ron Parameter LOW-level output voltage input clamping voltage input capacitance at gate off-state input/output capacitance on-state input/output capacitance ON-state resistance Conditions VCC = 3.0 V; VSREF = 1.365 V; VSn or VDn = 0.175 V; Iclamp = 15.2 mA II = -18 mA; VGREF = 0 V VI = 3 V or 0 V VO = 3 V or 0 V; VGREF = 0 V VO = 3 V or 0 V; VGREF = 3 V VI = 0 V; IO = 64 mA VGREF = 4.5 V VGREF = 3 V VGREF = 2.3 V VGREF = 1.5 V VI = 0 V; IO = 30 mA; VGREF = 1.5 V VI = 2.4 V; IO = 15 mA; VGREF = 4.5 V VI = 2.4 V; IO = 15 mA; VGREF = 3 V VI = 1.7 V; IO = 15 mA; VGREF = 2.3 V
[1] [2] All typical values are measured at Tamb = 25 C. Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch. ON-state resistance is determined by the lowest voltage of the two (Sn or Dn) terminals.
[2] [2] [2] [2] [2]
Min -
Typ[1] 260 56 7.4 18.6
Max 350 -1.2 5 -
Unit mV V A pF pF pF
gate input leakage current VI = 5 V; VGREF = 0 V
-
3.5 4.4 5.5 67 9 7 58 50
5 7 9 115 15 10 80 70

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10-bit bidirectional low voltage translator
12. Dynamic characteristics
12.1 Dynamic characteristics for translator-type application
Table 10. Dynamic characteristics Tamb = -40 C to +85 C; Vref = 1.365 V to 1.635 V; VCC1 = 3.0 V to 3.6 V; VCC2 = 2.36 V to 2.64 V; GND = 0 V; tr = tf 3.0 ns; unless otherwise specified. Refer to Figure 9. Symbol tPLH tPHL
[1] [2] [3]
Parameter LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay
Conditions Sn to Dn; Dn to Sn Sn to Dn; Dn to Sn
[2][3] [2][3]
Min 0.5 0.5
Typ[1] 1.5 1.5
Max 5.5 5.5
Unit ns ns
All typical values are measured at VCC1 = 3.3 V, VCC2 = 2.5 V, Vref = 1.5 V and Tamb = 25 C. Propagation delay guaranteed by characterization. Cio(on)(max) of 30 pF and Cio(off)(max) of 15 pF is guaranteed by design.
VI input VM VM GND tPHL0 test jig output HIGH-to-LOW LOW-to-HIGH VM tPHL tPHL1 DUT output HIGH-to-LOW LOW-to-HIGH VM tPLH1 VM VOL
002aac063
tPLH0 VCC2 VM tPLH VOL VCC2
VM = 1.5 V; VI = GND to 3.0 V
Fig 7.
The input (Sn) to output (Dn) propagation delays
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12.2 Dynamic characteristics for CBT-type application
Table 11. Dynamic characteristics Tamb = -40 C to +85 C; VGREF = 5 V 0.5 V; GND = 0 V; CL = 50 pF; unless otherwise specified. Refer to Figure 10. Symbol tPD
[1]
Parameter propagation delay
Conditions
[1]
Min -
Typ -
Max 250
Unit ps
This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON-state resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
3.0 V input 1.5 V tPLH 1.5 V 0V tPHL VOH output 1.5 V 1.5 V VOL
002aab664
tPD = the maximum of tPLH or tPHL. VM = 1.5 V; VI = GND to 3.0 V.
Fig 8.
Input (Sn) to output (Dn) propagation delays
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13. Test information
VCC1
200 k
VCC2
150
VCC2
150
VCC2
150
DREF
GREF
D1
D10 DUT
SREF
S1
S10 test jig
Vref pulse generator
002aac064
Fig 9.
Load circuit for translator-type applications
RL
S1
from output under test
CL 50 pF
500 RL 500
7V open GND
002aab667
Test data are given in Table 12. CL = load capacitance; includes jig and probe capacitance. RL = load resistance.
Fig 10. Load circuit for CBT-type application Table 12. Test tPD tPLZ, tPZL tPHZ, tPZH Test data Load CL 50 pF 50 pF 50 pF RL 500 500 500 open 7V open Switch
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10-bit bidirectional low voltage translator
14. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT355-1 (TSSOP24)
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HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm
SOT616-1
D
B
A
terminal 1 index area A A1 E c
detail X
e1
1/2 e
C b 12 vMCAB wMC 13 e y1 C y
e 7 L 6
Eh
1/2 e
e2
1
18
terminal 1 index area
24 Dh 0
19 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 12. Package outline SOT616-1 (HVQFN24)
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15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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15.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 13) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 13 and 14
Table 13. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 14. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
16. Abbreviations
Table 15. Acronym CDM CMOS DUT ESD GTL HBM I2C-bus LVTTL MM NMOS TTL TVC Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Gunning Transceiver Logic Human Body Model Inter IC bus Low Voltage Transistor-Transistor Logic Machine Model Negative-channel Metal Oxide Semiconductor Transistor-Transistor Logic Transceiver Voltage Clamps
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17. Revision history
Table 16. Revision history Release date 20080303 Data sheet status Product data sheet Change notice Supersedes GTL2010_5 Document ID GTL2010_6 Modifications:
* * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 7 "Limiting values[1]": deleted (old) table note [1] (statement is now in Section 18.3 "Disclaimers") Table 9 "Static characteristics": - Ron maximum value for condition VI = 0 V; IO = 64 mA; VGREF = 1.5 V changed from 105 to 115 - Symbol "IIH, gate input leakage" changed to "ILI(G), gate input leakage current"
GTL2010_5 (9397 750 13854) GTL2010_4 (9397 750 11458) GTL2010_3 (9397 750 11352) GTL2010_2 (9397 750 07462) GTL2010_1
20040728 20030502 20030401 20000830 19990405
Product data sheet Product data Product data Product specification Product specification
853-2153 29981 of 2003 May 01 853-2153 29603 of 2003 Feb 28 853-2153 24452 of 2000 Aug 30 -
GTL2010_4 GTL2010_3 GTL2010_2 GTL2010_1 -
GTL2010_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 3 March 2008
18 of 20
NXP Semiconductors
GTL2010
10-bit bidirectional low voltage translator
18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
18.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
GTL2010_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 3 March 2008
19 of 20
NXP Semiconductors
GTL2010
10-bit bidirectional low voltage translator
20. Contents
1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 8 8.1 8.2 8.3 8.4 9 10 11 12 12.1 12.2 13 14 15 15.1 15.2 15.3 15.4 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function selection. . . . . . . . . . . . . . . . . . . . . . . 4 Application design-in information . . . . . . . . . . 5 Bidirectional translation. . . . . . . . . . . . . . . . . . . 5 Unidirectional down translation. . . . . . . . . . . . . 6 Unidirectional up translation . . . . . . . . . . . . . . . 6 Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Dynamic characteristics for translator-type application. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Dynamic characteristics for CBT-type application. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Soldering of SMD packages . . . . . . . . . . . . . . 15 Introduction to soldering . . . . . . . . . . . . . . . . . 15 Wave and reflow soldering . . . . . . . . . . . . . . . 15 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 March 2008 Document identifier: GTL2010_6

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